1. Field of the Invention
The present invention relates to a recording head drive control apparatus for use in a recording apparatus which forms characters, symbols, figures, etc. on a recording medium.
2. Description of the Prior Art
Conventionally, in non-impact recording apparatuses, for example, in liquid jet recording apparatuses, they are provided with a switching circuit to control the operation and non-operation of the recording head and a drive circuit to apply a drive voltage or current to the recording head in accordance with the image data input and they are constituted in a manner such that when the recording head is not driven during the recording operation, the switching circuit is controlled so that the drive voltage or current is not applied to the recording head.
However, the recording head driving apparatus with such a construction requires such a switching circuit and drive circuit for every recording head. Therefore, in the image forming apparatus employing this driving apparatus, particularly, in the multihead recording apparatus such as a full color printer or the like, the circuitry becomes complicated as will be explained later in conjunction with FIGS. 1 to 3, so that this causes the apparatus to be increased in size and the manufacturing cost to be raised.
The conventional recording apparatus will now be described hereinbelow.
FIG. 1 shows a fundamental arrangement of the conventional recording head drive circuit, in which a reference numeral 1 denotes a drive voltage source; 2 is a pnp switching transistor as an example of a switching element; 3 is a piezoelectric element as an example of a liquid jet head driving member; and 4 to 7 are resistors. When a control pulse of the polarity shown in the diagram is now applied to the resistor 7, the piezoelectric element 3 contracts since it is charged in the polarizing direction thereof through the resistor 4 by a drive voltage of the voltage source 1, so that the volume of a pressure chamber in the jet head is reduced and a recording liquid droplet is discharged. Upon completion of the control pulse, the charges accumulated in the piezoelectric element 3 are discharged through the resistor 5. Although the arrangement of the recording head drive circuit has been variously improved and modified, the essential point is that the recording image is formed by controlling the discharge and stop of the recording liquid by means of the liquid jet head and the like in response to the on-off operations of the switching element. In addition, since the construction of the liquid jet head and means for discharging the recording liquid droplet thereof are well known to those skilled in the art, their detailed descriptions are omitted here.
FIG. 2 shows an example of the conventional recording apparatus provided with the recording head drive circuit of FIG. 1. In FIG. 2, a numeral 11 indicates a voltage converting table circuit; 12 is a line memory; 13 a latch circuit; 14Y to 14BK are D-A converters for every chrominance signal of the recording liquid; 22Y to 22BK are drive voltage amplifiers which respectively correspond to the D-A converters 14Y to 14BK; 23Y to 23BK are NAND gates which are respectively provided for every chrominance signal; and 24 is a timing pulse generator. A timing pulse T.sub.p generated from the timing pulse generator 24 and signals .phi..sub.Y -.phi..sub.BK representing that the recording operations are performed with regard to the recording heads for every chrominance signal are supplied to the NAND gates 23Y-23BK. Numerals 15Y to 15BK are recording head drive circuits which are controlled in response to outputs of the NAND gates 23Y-23BK and drive a recording head 16Y and the like in response to the outputs of the amplifiers 22Y-22BK.
As will be explained later with respect to FIG. 4, the front stage of the voltage converting table circuit 11 is constituted in the manner such that image signals R, G and BL are input to A-D converters and are converted to digital signals at predetermined timings on the basis of the sync signals and then they are input to an image processing circuit. In the image processing circuit, image signals R', G' and BL' which were converted to the digital signals are further converted to chrominance signals Y, M, C and BK of the recording liquids. These chrominance signals are converted by the voltage converting table circuit 11 to digital data corresponding to the voltage values which are applied to the recording heads. These data are input to the line memory 12 and the data of the necessary capacity are stored therein. These data stored are fetched into the latch circuit 13 at a predetermined timing and are converted to the analog signals by the D-A converters 14Y-14BK. These analog signals are input to the recording head drive circuits 15Y-15BK. The internal arrangement of each of these drive circuits is the same as the drive circuit of FIG. 1 as typically shown in FIG. 2 with regard to 15Y. Namely, the output of the NAND gate 23Y or the like is supplied to the base of the switching transistor and the output of the amplifier 22Y or the like is supplied to the emitter thereof, and the piezoelectric element 16Y or the like is driven similarly to the circuit of FIG. 1.
In the system shown in FIG. 2, the gate circuits (in this example, the NAND gates 23Y-23BK) in addition to the amplifiers 22Y-22BK are needed among the D-A converters 14Y-14BK and the drive circuits 15Y-15BK for every recording head. Thus, the circuit arrangement becomes complicated in the multihead recording apparatus and this causes the apparatus to be increased in size and the cost to be raised.
FIG. 3 shows another example of the recording apparatus provided with the conventional recording head control system. Although the latch circuit 13 and the subsequent circuit arrangement are shown in this diagram, the front stage thereof is fundamentally similar to that of FIG. 2. In the apparatus of FIG. 3, a preset register 25 is provided, and the magnitude of a digital value A of each chrominance signal which is an output of the latch circuit 13 and the magnitude of an output B of the preset register 25 are compared by a comparator 26Y or the like. When A&gt;B, an output of the comparator 26Y or the like becomes a high level and the NAND gate 23Y or the like is controlled in response to this output and the timing pulse which is output from the timing pulse generator 24. Also, in FIG. 3, numerals 15'M, 15'C and 15'BK represent the circuits each totally corresponding to the D-A converter 14Y, amplifier 22Y, comparator 26Y, NAND gate 23Y, and recording head drive circuit 15Y for the chrominance signal Y with respect to the chrominance signals M, C and BK. In the apparatus of FIG. 3, the circuit arrangement obviously becomes complicated similarly to the apparatus of FIG. 2.
As described above, the conventional driving apparatus requires the switching circuit and drive circuit for each recording head. Also, it is necessary to constitute the apparatus such that no drive voltage or current is applied to the recording head by controlling the switching circuit when the recording is not done. Therefore, the circuit arrangement becomes complicated.